T89C5121-ICUIL Atmel, T89C5121-ICUIL Datasheet - Page 81

• Manufacturer Part Number: T89C5121-ICUIL
• Description: IC 8051 MCU W/SMART CARD 24SSOP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C5121-ICUIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: Flash RAM
• Eeprom Size: 16K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 5.4 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: Q1468934; T89C5121-ICSIL; T89C5121-ICSIL

Serial I/O Port
Framing Error Detection
4164G–SCR–07/06
The serial I/O port is entirely compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-
taneously and at different baud rates.
Serial I/O port includes the following enhancements:
•
•
Figure 32. Serial I/O UART Port Block Diagram
Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register.
Figure 33. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset clear FE bit. Subsequently received frames with valid stop bits
cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last
data bit (See Figure 34 and Figure 35).
Framing error detection and Automatic Address Recognition
Internal Baud Rate Generator
TXD
RXD
SM0/FE
SMOD1
Transmitter
SMOD0
SBUF
SM1
SM2
Mode 0 Transmit
-
IB Bus
Write SBUF
RI
POF
REN
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
To UART framing error control
TI
TB8
GF1
Shift register
RB8
GF0
Receiver
Receive
SBUF
PD
TI
Interrupt Request
Serial Port
A/T8xC5121
Read SBUF
Load SBUF
IDL
RI
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