ATMEGA169V-1MC Atmel, ATMEGA169V-1MC Datasheet - Page 80
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ATMEGA169V-1MC
Manufacturer Part Number
ATMEGA169V-1MC
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-1MC
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Definitions
Timer/Counter Clock
Sources
Counter Unit
80
ATmega169V/L
event will also set the Compare Flag (OCF0A) which can be used to generate an Output
Compare interrupt request.
Many register and bit references in this section are written in general form. A lower case
“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the
Output Compare unit channel, in this case channel A. However, when using the register
or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in Table 48 are also used extensively throughout the document.
Table 48. Definitions
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select
(CS02:0) bits located in the Timer/Counter Control Register (TCCR0A). For details on
clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on
page 93.
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 27 shows a block diagram of the counter and its surroundings.
Figure 27. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNTn
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The
assignment is dependent on the mode of operation.
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
direction
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
T0
in the following.
Clock Select
( From Prescaler )
Detector
Edge
2514H–AVR–05/03
Tn
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