ATMEGA644V-10AU Atmel, ATMEGA644V-10AU Datasheet - Page 126

• Manufacturer Part Number: ATMEGA644V-10AU
• Description: IC AVR MCU FLASH 64K 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

126
ATmega644
Table 14-3
PWM mode.
Table 14-3.
Note:
Table 14-4
correct or the phase and frequency correct, PWM mode.
Table 14-4.
Note:
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes.
COMnA1/COMnB1
COMnA1/COMnB1
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set.
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at TOP.
“14.9.3” on page 117.
Section “14.9.4” on page 119.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
Compare Output Mode, Fast PWM
Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
(1)
COMnA0/COMnB0
COMnA0/COMnB0
for more details.
Table
0
1
0
1
0
1
0
1
14-5. Modes of operation supported by the Timer/Counter
for more details.
(See Section “14.9” on page
Description
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OCnA/OCnB on Compare Match, set
OCnA/OCnB at BOTTOM (non-inverting mode)
Set OCnA/OCnB on Compare Match, clear
OCnA/OCnB at BOTTOM (inverting mode)
Description
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 9 or 11: Toggle OCnA on Compare
Match, OCnB disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OCnA/OCnB on Compare Match when up-
counting. Set OCnA/OCnB on Compare Match when
downcounting.
Set OCnA/OCnB on Compare Match when up-
counting. Clear OCnA/OCnB on Compare Match
when downcounting.
(1)
116.).
See Section
2593N–AVR–07/10
See