ATMEGA644V-10AU Atmel, ATMEGA644V-10AU Datasheet - Page 248

• Manufacturer Part Number: ATMEGA644V-10AU
• Description: IC AVR MCU FLASH 64K 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.9
21.9.1
248
Register Description
ATmega644
ADMUX – ADC Multiplexer Selection Register
• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Table 21-3.
Note:
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see
page
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See
bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 21-4.
Bit
(0x7C)
Read/Write
Initial Value
MUX4..0
00000
00001
00010
00011
00100
00101
REFS1
0
0
1
1
251.
If 10x og 200x gain is selected, only 2.56V should be used as Internal Voltage Reference.
REFS0
Single Ended
Input
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
Voltage Reference Selections for ADC
Input Channel and Gain Selections
REFS1
0
1
0
1
R/W
7
0
Voltage Reference Selection
AREF, Internal Vref turned off
AVCC with external capacitor at AREF pin
Internal 1.1V Voltage Reference with external capacitor at AREF pin
Internal 2.56V Voltage Reference with external capacitor at AREF pin
REFS0
R/W
6
0
ADLAR
Positive Differential
Input
N/A
R/W
5
0
MUX4
R/W
4
0
”ADCL and ADCH – The ADC Data Register” on
MUX3
R/W
3
0
MUX2
Negative Differential
Input
R/W
2
0
Table 21-4
Table
MUX1
R/W
1
0
21-3. If these bits are
for details. If these
MUX0
R/W
0
0
2593N–AVR–07/10
ADMUX
Gain