AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 526
![IC MCU 256KB FLASH 100TFBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
AT91SAM7X256B-CU
Manufacturer Part Number
AT91SAM7X256B-CU
Description
IC MCU 256KB FLASH 100TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X256B-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
91S
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, Ethernet, SPI, I2S, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
62
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Package
100TFBGA
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
On-chip Adc
8-chx10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Figure 36-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages
36.7.3.5
6120H–ATARM–17-Feb-09
(CAN_MSRx)
(CAN_MSRx)
(CAN_MSRy)
(CAN_MSRy)
(CAN_MSRz)
(CAN_MSRz)
CAN BUS
MRDY
MRDY
MRDY
MMI
MMI
MMI
Transmission Handling
A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been config-
ured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled.
After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set
until the first command is sent. When the MRDY flag is set, the software application can prepare
a message to be sent by writing to the CAN_MDx registers. The message is sent once the soft-
ware asks for a transfer command setting the MTCR bit and the message data length in the
CAN_MCRx register.
The MRDY flag remains at zero as long as the message has not been sent or aborted. It is
important to note that no access to the mailbox data register is allowed while the MRDY flag is
cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be
masked depending on the mailbox flag in the CAN_IMR global register.
It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field.
The answer to the remote frame is handled by another reception mailbox. In this case, the
device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote
frame emission and the answer reception using only one mailbox configured in Consumer Mode.
Refer to the section
Several messages can try to win the bus arbitration in the same time. The message with the
highest priority is sent first. Several transfer request commands can be generated at the same
time by setting MBx bits in the CAN_TCR register. The priority is set in the PRIOR field of the
CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is
possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same
priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox 0 and
Message s1
Reading CAN_MDH & CAN_MDL for mailboxes x, y and z
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz
Message s2
“Remote Frame Handling” on page
AT91SAM7X512/256/128 Preliminary
Message s3
Writing MBx MBy MBz in CAN_TCR
Message s4
527.
Buffer split in 4 messages
526
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