AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 585
![IC MCU 256KB FLASH 100TFBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
AT91SAM7X256B-CU
Manufacturer Part Number
AT91SAM7X256B-CU
Description
IC MCU 256KB FLASH 100TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X256B-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
91S
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
CAN, Ethernet, SPI, I2S, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
62
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Package
100TFBGA
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
On-chip Adc
8-chx10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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37.5.4
Register Name:
Access Type:
This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1
to them. It is not possible to set a bit to 1 by writing to the register.
• UBR: Used Bit Read
Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.
• COL: Collision Occurred
Set by the assertion of collision. Cleared by writing a one to this bit.
• RLE: Retry Limit exceeded
Cleared by writing a one to this bit.
• TGO: Transmit Go
If high transmit is active.
• BEX:
If the buffers run out during transmission of a frame, then transmission stops, FCS shall be bad and tx_er asserted. Cleared
by writing a one to this bit.
• COMP: Transmit Complete
Set when a frame has been transmitted. Cleared by writing a one to this bit.
• UND: Transmit Underrun
Set when transmit DMA was not able to read data from memory, either because the bus was not granted in time, because
a not OK hresp(bus error) was returned or because a used bit was read midway through frame transmission. If this
occurs, the transmitter forces bad CRC. Cleared by writing a one to this bit.
6120H–ATARM–17-Feb-09
31
23
15
–
–
–
7
–
Buffers exhausted mid frame
Transmit Status Register
UND
30
22
14
EMAC_TSR
–
–
–
6
Read-write
COMP
29
21
13
–
–
–
5
AT91SAM7X512/256/128 Preliminary
BEX
28
20
12
–
–
–
4
TGO
27
19
11
–
–
–
3
RLE
26
18
10
–
–
–
2
COL
25
17
–
–
9
–
1
UBR
24
16
–
–
8
–
0
585
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