AT91SAM7X256B-CU Atmel, AT91SAM7X256B-CU Datasheet - Page 677

• Manufacturer Part Number: AT91SAM7X256B-CU
• Description: IC MCU 256KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X256B-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: 91S
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, Ethernet, SPI, I2S, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• On-chip Adc: 8-chx10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6120H–ATARM–17-Feb-09
Version
6120E
6120D
6120C
6120B
6120A
Comments
04-Apr-06
The following errata have been added:
Section 41.2.3.2 ”EMAC: Possible Event Loss when Reading EMAC_ISR”
Section 41.2.3.3 ”EMAC: Possible Event Loss when Reading the Statistics Register Block”
Section 41.2.7.3 ”SPI: SPCK Behavior in Master Mode”
Section 41.2.4.1 ”PIO: Leakage on PB27 -
03-Feb-06
Section 41. ”AT91SAM7X512/256/128 Errata”
Device package/product number changed
Section 41.2.3 ”Ethernet MAC (EMAC)”
The sections listed below have been added to the Errata:
Section 41.2.5 ”Pulse Width Modulation Controller (PWM)”
Section 41.2.7 ”Serial Peripheral Interface (SPI)”
Section 41.2.8 ”Synchronous Serial Controller (SSC)”
Section 41.2.9 ”Two-wire Interface (TWI)”
Section 41.2.10 ”Universal Synchronous Asynchronous Receiver Transmitter (USART)”
26-Oct-05
Replaced
17-Oct-05
Updated product functionalities in
on page
Corrected PLL output range maximum value in
Section 18.3.2.1 “Internal Memory Mapping” on page 95
Characteristics,” on page
Updated information in Power Supplies on page 9
Updated field Part Number in
Updated Chip ID in
Removed references to PGMEN2 in
Updated “ARCH: Architecture Identifier” in Debug Unit with new values for AT91SAM7XCxx series and
AT91SAM7Xxx series.
Updated CAN bit timing configuration in
and in
Added
Updated AT91SAM7X Ordering information.
10-Oct-05
Section 36.8.6 “CAN Baudrate Register” on page
Section 38.8.4 “EMAC Characteristics” on page
29, and Figure 11-1 on page 27
Section 29. “Two-wire Interface (TWI)” on page
Section 9.5 “Debug Unit” on page 29
623.
Section 12.5.5 “ID Code Register” on page
“Features” on page
Section 20. “Fast Flash Programming Interface (FFPI)” on page
RMII mode is not functional
Section 36.6.4.1 “CAN Bit Timing Configuration” on page 512
AT91SAM7X512/256/128 Preliminary
PB30”: worst case leakage changed to 9 µA
Section 9.2 “Clock Generator” on page
1,
630.
Figure 2-1 on page
545.
and
and in
281.
Table 38-12, “Phase Lock Loop
Section 12.5.3 “Debug Unit” on page
55.
4,
Section 9.5 “Debug Unit”
27,
Figure 18-3
119.
48.
in
Change
Request
Ref.
#2455
#2605
#1767
05-516
05-456
05-491
05-472
05-464
05-459
05-419
05-469
05-470
First issue
677