LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 186

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
11.6.18 UART RS-485 Address Match register (U0RS485ADRMATCH - 0x4000
11.6.19 UART1 RS-485 Delay value register (U0RS485DLY - 0x4000 8054)
11.6.20 RS-485/EIA-485 modes of operation
Table 205. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit
8050)
The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
Table 206. UART RS-485 Address Match register (U0RS485ADRMATCH - address
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
Table 207. UART RS-485 Delay value register (U0RS485DLY - address 0x4000 8054) bit
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
Bit
31:6 -
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
Symbol
DLY
-
Symbol
ADRMATCH
-
description
0x4000 8050) bit description
description
All information provided in this document is subject to legal disclaimers.
Description
Contains the direction control (RTS or DTR) delay value. This
register works in conjunction with an 8-bit counter.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Value
0
1
-
…continued
Description
Contains the address match value.
Reserved
Rev. 2 — 7 July 2010
Description
The direction control pin will be driven to logic ‘0’
when the transmitter has data to be sent. It will be
driven to logic ‘1’ after the last bit of data has been
transmitted.
The direction control pin will be driven to logic ‘1’
when the transmitter has data to be sent. It will be
driven to logic ‘0’ after the last bit of data has been
transmitted.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x00
-
Reset value
0x00
NA
Reset
value
NA
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