LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 22
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
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Quantity
Price
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LPC1313FBD48,151
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Manufacturer:
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UM10375
User manual
3.5.14 USB PLL clock source update enable register
3.5.15 Main clock source select register
3.5.16 Main clock source update enable register
This register updates the clock source of the USB PLL with the new input clock after the
USBPLLCLKSEL register has been written to. In order for the update to take effect at the
USB PLL input, first write a zero to the USBPLLUEN register and then write a one to
USBPLLUEN.
Remark: The system oscillator must be selected in the USBPLLCLKSEL register in order
to use the USB PLL, and this register must be toggled to update the USB PLL clock with
the system oscillator.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 19.
This register selects the main system clock which can be either any input to the system
PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators
directly. The main system clock clocks the core, the peripherals and memories, and
optionally the USB block.
The MAINCLKUEN register (see
the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 20.
This register updates the clock source of the main clock with the new input clock after the
MAINCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.
Bit
0
31:1
Bit
1:0
31:2
Symbol
ENA
-
Symbol
SEL
-
USB PLL clock source update enable register (USBPLLCLKLUEN, address
0x4004 804C) bit description
Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit
description
All information provided in this document is subject to legal disclaimers.
Value
00
01
10
11
-
Value
0
1
-
Rev. 2 — 7 July 2010
Description
Cock source for main clock
IRC oscillator
Input clock to system PLL
WDT oscillator
System PLL clock out
Reserved
Description
Enable USB PLL clock source update
No change
Update clock source
Reserved
Section
3.5.16) must be toggled from LOW to HIGH for
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x00
0x00
Reset value
0x0
0x00
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