LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 206

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
12.10.7 Serial clock generator
The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the longest “spaces”.
Figure 29
A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.
This programmable clock pulse generator provides the SCL clock pulses when the I
block is in the master transmitter or master receiver mode. It is switched off when the I
block is in a slave mode. The I
Fig 28. Arbitration procedure
Fig 29. Serial clock synchronization
(1) Another device transmits serial data.
(2) Another device overrules a logic (dotted line) transmitted this I
(3) This I
(1) Another device pulls the SCL line low before this I
(2) Another device continues to pull the SCL line low after this I
(3) The SCL line is released , and the clock generator begins timing the HIGH time.
low. Arbitration is lost, and this I
transmitted. This I
the new master once it has won arbitration.
device effectively determines the (shorter) HIGH period.
released SCL. The I
effectively determines the (longer) LOW period.
SDA line
SCL line
shows the synchronization procedure.
SDA line
SCL line
2
C is in Slave Receiver mode but still generates clock pulses until the current byte has been
All information provided in this document is subject to legal disclaimers.
2
Rev. 2 — 7 July 2010
C will not generate clock pulses for the next byte. Data on SDA originates from
2
C clock generator is forced to wait until SCL goes HIGH. The other device
(1)
1
period
high
2
C block will stretch the SCL space duration after a byte has
2
C output clock frequency and duty cycle is programmable
(1)
(1)
2
2
C enters Slave Receiver mode.
period
low
(2)
3
(2)
(3)
Chapter 12: LPC13xx I2C-bus controller
4
2
C has timed a complete high time. The other
(1)
2
C has timed a complete low time and
(3)
2
C master by pulling the SDA line
8
UM10375
© NXP B.V. 2010. All rights reserved.
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