LPC1754FBD80,551 NXP Semiconductors, LPC1754FBD80,551 Datasheet - Page 14

IC ARM CORTEX MCU 128K 80-LQFP

LPC1754FBD80,551

Manufacturer Part Number
LPC1754FBD80,551
Description
IC ARM CORTEX MCU 128K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets

Specifications of LPC1754FBD80,551

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
52
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Cpu Family
LPC17xx
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
100MHz
Total Internal Ram Size
32KB
# I/os (max)
52
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.4/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4790
935287913551

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NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
7.6 Memory map
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permitted by the region setting, will cause the Memory Management Fault
exception to take place.
The LPC1759/58/56/54/52/51 incorporate several distinct memory regions, shown in the
following figures.
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
All information provided in this document is subject to legal disclaimers.
Figure 3
Rev. 6.01 — 11 March 2011
shows the overall map of the entire address space from the
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
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