LPC1764FBD100,551 NXP Semiconductors, LPC1764FBD100,551 Datasheet - Page 60

IC ARM CORTEX MCU 128K 100-LQFP

LPC1764FBD100,551

Manufacturer Part Number
LPC1764FBD100,551
Description
IC ARM CORTEX MCU 128K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets

Specifications of LPC1764FBD100,551

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
70
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME, IRD-LPC1768-DEV, KSK-LPC1768-JL
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Package
100LQFP
Device Core
ARM Cortex M3
Family Name
LPC1700
Maximum Speed
100 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4793
935287919551

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1764FBD100,551
Quantity:
9 999
Part Number:
LPC1764FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
11.9 SPI
Table 17.
T
[1]
[2]
Symbol
T
T
t
t
SPI master
t
t
t
t
SPI slave
t
t
t
t
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIQV
SPIOH
SPIDSU
SPIDH
SPIQV
SPIOH
amb
Fig 22.
cy(PCLK)
SPICYC
T
processor clock CCLK.
Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %)
edge of the data signal (MOSI or MISO).
=
SPICYC
40
SPI master timing (CPHA = 1)
°
= (T
Dynamic characteristics of SPI pins
C to +85
SCK (CPOL = 0)
SCK (CPOL = 1)
Parameter
PCLK cycle time
SPI cycle time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
cy(PCLK)
All information provided in this document is subject to legal disclaimers.
MOSI
MISO
°
× n) ± 0.5 %, n is the SPI clock divider value (n ≥ 8); PCLK is derived from the
C.
Rev. 6.01 — 11 March 2011
LPC1769/68/67/66/65/64/63
DATA VALID
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
T
DATA VALID
SPICYC
t
SPIQV
Min
10
79.6
0.485 × T
0
2 × T
2 × T
2 × T
0
2 × T
2 × T
2 × T
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
cy(PCLK)
32-bit ARM Cortex-M3 microcontroller
t
SPICYC
t
SPICLKH
SPIDSU
− 5
+ 30
+ 5
+ 5
+ 35
+ 15
DATA VALID
DATA VALID
t
SPICLKL
t
SPIDH
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
0.515 × T
-
-
-
-
-
-
-
-
t
002aad986
© NXP B.V. 2011. All rights reserved.
SPIOH
SPICYC
60 of 79
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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