LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 347
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
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Table 315. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xFFE0 C240) bit allocation
Reset value: 0x0000 0000
Table 316. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xFFE0 C240) bit description
UM10237_4
User manual
Bit
31:0
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
See
USBEpIntPri
bit allocation
table above
EP15TX
9.5.1 EP RAM requirements
EP11TX
EP7TX
EP3TX
9.5 Endpoint realization registers
31
23
15
7
Value
0
1
The registers in this group allow realization and configuration of endpoints at run time.
The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM
dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has
space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends
on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by
the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the
MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next
word boundary. Also, each buffer has one word header showing the size of the packet
length received.
The EP_ RAM space (in words) required for the physical endpoint can be expressed as
where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.
EP15RX
EP11RX
EP7RX
EP3RX
30
22
14
6
Description
The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 0
The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
EP14TX
EP10TX
EP6TX
EP2TX
EPRAMspace
29
21
13
5
Rev. 04 — 26 August 2009
EP10RX
EP6RX
EP2RX
E14RX
28
20
12
4
=
⎛
⎝
MaxPacketSize
------------------------------------------------- -
EP13TX
Chapter 13: LPC24XX USB device controller
EP9TX
EP5TX
EP1TX
27
19
11
3
4
+
EP13RX
3
EP9RX
EP5RX
EP1RX
+
26
18
10
2
1
⎞
⎠
×
dbstatus
EP12TX
EP8TX
EP4TX
EP0TX
25
17
UM10237
9
1
© NXP B.V. 2009. All rights reserved.
Reset value
EP12RX
EP8RX
EP4RX
EP0RX
347 of 792
24
16
8
0
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