LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 431
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
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LPC2470FET208,551
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Part Number:
LPC2470FET208,551
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NXP Semiconductors
UM10237_4
User manual
4.6 UARTn FIFO Control Register (U0FCR - 0xE000 C008, U2FCR -
4.7 UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR -
THRE = 1 and there have not been at least two characters in the UnTHR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UARTn THR FIFO has held two or more characters at one time and
currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or
a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).
0xE007 8008, U3FCR - 0xE007 C008, Write Only)
The UnFCR controls the operation of the UARTn Rx and TX FIFOs.
Table 385. UARTn FIFO Control Register (U0FCR - address 0xE000 C008,
0xE007 800C, U3LCR - 0xE007 C00C)
The UnLCR determines the format of the data character that is to be transmitted or
received.
Bit
0
1
2
5:3
7:6
Symbol
FIFO Enable 0
RX FIFO
Reset
TX FIFO
Reset
-
RX Trigger
Level
U2FCR - 0xE007 8008, U3FCR - 0xE007 C008, Write Only) bit description
Value
1
0
1
0
1
0
00
01
10
11
Rev. 04 — 26 August 2009
Description
UARTn FIFOs are disabled. Must not be used in the
application.
Active high enable for both UARTn Rx and TX
FIFOs and UnFCR[7:1] access. This bit must be set
for proper UARTn operation. Any transition on this
bit will automatically clear the UARTn FIFOs.
No impact on either of UARTn FIFOs.
Writing a logic 1 to UnFCR[1] will clear all bytes in
UARTn Rx FIFO and reset the pointer logic. This bit
is self-clearing.
No impact on either of UARTn FIFOs.
Writing a logic 1 to UnFCR[2] will clear all bytes in
UARTn TX FIFO and reset the pointer logic. This bit
is self-clearing.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
These two bits determine how many receiver
UARTn FIFO characters must be written before an
interrupt is activated.
Trigger level 0 (1 character or 0x01)
Trigger level 1 (4 characters or 0x04)
Trigger level 2 (8 characters or 0x08)
Trigger level 3 (14 characters or 0x0E)
Chapter 16: LPC24XX UART0/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0
0
0
NA
0
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