LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 667
LPC2470FET208,551
Manufacturer Part Number
LPC2470FET208,551
Description
IC ARM7 MCU LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FET208,551
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4362
935284071551
LPC2470FET208-S
935284071551
LPC2470FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
Exar
Quantity:
92
Company:
Part Number:
LPC2470FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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1. Basic configuration
2. Features
3. Description
4. Pin description
UM10237_4
User manual
The ADC is configured using the following registers:
Basic clocking for the A/D converters is provided by the APB clock (PCLK). A
programmable divider is included in each converter, to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. A fully accurate conversion
requires 11 of these clocks.
Table 28–591
1. Power: In the PCONP register
2. Clock: In the PCLK_SEL0 register
3. Pins: Select ADC pins and pin modes in registers PINSELn and PINMODEn (see
4. Interrupts: To enable interrupts in the ADC, see
•
•
•
•
•
•
•
•
UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
Rev. 04 — 26 August 2009
Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,
and then enable the ADC in the AD0CR register (bit PDN)
the ADC, first clear the PDN bit, and then clear the PCADC bit.
clock for the ADC, see
Section
in the VIC using the VICIntEnable register
10 bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3 V.
10 bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
9–5).
gives a brief summary of each of ADC related pins.
Rev. 04 — 26 August 2009
Table 28–593
(Table
(Table
bits CLKDIV.
4–63), set bits PCADC.
4–56), select PCLK_ADC. To scale the
(Section
Table
7–3.4).
28–596. Interrupts are enabled
Table
28–593. To disable
© NXP B.V. 2009. All rights reserved.
User manual
667 of 792
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