LPC2470FET208,551 NXP Semiconductors, LPC2470FET208,551 Datasheet - Page 736

• Manufacturer Part Number: LPC2470FET208,551
• Description: IC ARM7 MCU LCD 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2470FET208,551

• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2470U
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4362; 935284071551; LPC2470FET208-S

NXP Semiconductors
10. GPDMA data flow
UM10237_4
User manual
9.1 Hardware interrupt sequence flow
9.2 Interrupt polling sequence flow
When a DMA interrupt request occurs, the Interrupt Service Routine needs to:
Used when the GPDMA interrupt request signal is either masked out, disabled in the
interrupt controller or disabled in the processor. When polling the GPDMA, you must:
This section describes the GPDMA data flow sequences for the four allowed transfer
types:
Each transfer type can have either the peripheral or the GPDMA as the flow controller so
there are eight possible control scenarios.
Table 32–676
1. Read the DMACIntStatus Register to determine which channel generated the
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
3. Read the DMACIntErrorStatus Register to determine whether the interrupt was
4. Service the interrupt request.
5. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
1. Read the DMACIntStatus Register. If none of the bits are HIGH repeat this step,
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
3. Service the interrupt request.
4. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
•
•
•
•
interrupt. If more than one request is active it is recommended that the highest priority
channels be checked first.
generated due to the end of the transfer (terminal count). A HIGH bit indicates that the
transfer completed.
generated due to an error occurring. A HIGH bit indicates that an error occurred.
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
otherwise go to step 2. If more than one request is active it is recommended that the
highest priority channels be checked first.
generated due to the end of the transfer (terminal count). A HIGH bit indicates that the
transfer completed.
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
Memory-to-peripheral.
Peripheral-to-memory.
Memory-to-memory.
Peripheral-to-peripheral.
indicates the request signals used for each type of transfer.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
UM10237
© NXP B.V. 2009. All rights reserved.
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