EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 11

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

Reset and Power Management
The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.
Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.
The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).
Hardware Debug Interface
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
12-Channel DMA Controller
The DMA module contains 12 separate DMA channels.
These may be used for peripheral-to-memory or
memory-to-peripheral
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
The request bus is a collection of requests, Serial Audio
and
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be
DS667PP3
PRSTn
RSTOn
EGPIO[15]
EGPIO[13:0]
FGPIO[7]
FGPIO[5]
FGPIO[0]
TCK
TDI
TDO
TMS
TRSTn
Pin Mnemonic
Pin Mnemonic
Pin Mnemonic
Table P. Reset and Power Management Pin Assignments
Table O. General Purpose Input/Output Pin Assignment
UARTs.
independently programmed to increment,
Table Q. Hardware Debug Interface
Each
Expanded General Purpose Input / Output
Pins with Interrupts
Expanded General Purpose Input / Output
Pins with Interrupts
Power On Reset
User Reset In/Out – Open Drain –
Preserves Real Time Clock value
JTAG Clock
JTAG Data In
JTAG Data Out
JTAG Test Mode Select
JTAG Port Reset
DMA
access.
Pin Name - Description
Pin Name - Description
Pin Name - Description
channel can
Two
Copyright 2004 Cirrus Logic (All Rights Reserved)
of
these
be
used
are
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
ARM9 SOC with Ethernet, USB, Display and Touchscreen
EP9307
11