EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 9

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

Universal Asynchronous
Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two
provide asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. A third IrDA
compatible UART is also supplied.
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Internal Boot ROM
The Internal 16 Kbyte ROM allows booting from FLASH
memory, SPI or UART.
DS667PP3
TXD0
RXD0
CTSn
DSRn/DCDn
DTRn
RTSn
EGPIO[0]/RI
TXD1/SIROUT
RXD1/SIRIN
TXD2
RXD2
TENn
Table H. Universal Asynchronous Receiver / Transmitters Pin
UART1 supports modem bit rates up to 115.2 Kbps,
supports HDLC and includes a 16 byte FIFO for
receive and a 16 byte FIFO for transmit. Interrupts are
generated on Rx, Tx and modem status change.
UART2 contains an IrDA encoder operating at either
the slow (up to 115 Kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16
byte FIFO for receive and a 16 byte FIFO for transmit.
UART3 supports HDLC and includes a 16 byte FIFO
for receive and a 16 byte FIFO for transmit. Interrupts
are generated on Rx and Tx.
Pin Mnemonic
assemble
the
Assignments
UART1 Transmit
UART1 Receive
UART1 Clear To
Send / Transmit Enable
UART1 Data Set
Ready / Data Carrier Detect
UART1 Data Terminal Ready
UART1 Ready To Send
UART1 Ring Indicator
UART2 Transmit / IrDA
Output
UART2 Receive / IrDA Input
UART3 Transmit
UART3 Receive
HDLC3 Transmit Enable
frame
Pin Name - Description
in
Copyright 2004 Cirrus Logic (All Rights Reserved)
memory
before
®
Triple Port USB Host
The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tiered-
start” topology.
This includes the following features:
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•
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The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
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Two-Wire Interface With EEPROM Support
The two-wire interface provides communication and
control for EEPROM devices.
USBp[2:0]
USBm[2:0]
EECLK
EEDATA
Table J. Two-Wire Port with EEPROM Support Pin Assignments
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Pin Mnemonic
Compliance with the USB 2.0 specification
Compliance with the Open HCI Rev 1.0 specification
Supports both low speed (1.5 Mbps) and full speed
(12 Mbps) USB device connections
Root HUB integrated with 3 downstream USB ports
Transceiver buffers integrated, over-current protection
on ports
Supports power management
Operates as a master on the bus
Fetches endpoint descriptors and transfer descriptors
Accesses endpoint data from system memory
Accesses the HC communication area
Writes status and retire transfer descriptor
Pin Mnemonic
Table I. Triple Port USB Host Pin Assignments
EEPROM / Two-Wire
Interface Clock
EEPROM / Two-Wire
Interface Data
Pin Name - Description
USB Positive signals
USB Negative Signals
Pin Name - Description
General
Purpose I/O
General
Purpose I/O
Alternative
Usage
EP9307
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