EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 19

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

Static Memory Single Word Read Cycle
DS667PP3
AD setup to RDn assert time
AD hold from RDn deassert time
RDn assert time
CSn assert to RDn assert delay time
CSn deassert to RDn deassert delay time
CSn assert to DQMn assert delay time
CSn deassert to DQMn deassert delay time
DA setup to RDn deassert time
DA hold from RDn deassert time
See
DQMn
W AIT
W Rn
CSn
RDn
“Timing Conditions” on page 14
AD
DA
Parameter
Figure 6. Static Memory Single Word Read Cycle Timing Measurement
for definition of HCLK.
Copyright 2004 Cirrus Logic (All Rights Reserved)
t
ADs
Symbol
t
t
t
DQMd
DQMh
RDpw
t
t
t
t
t
t
ADh
RDd
RDh
DAh
ADs
DAs
t
t
R Dd1
D QMd1
Min
0
-
-
-
-
-
-
-
-
ARM9 SOC with Ethernet, USB, Display and Touchscreen
t
R D pw
t
HCLK
t
t
HCLK
× (WST1 + 2)
HCLK
Typ
5
0
0
0
0
0
+ 6
× 2
t
DAs
t
HCLK
Max
-
-
-
-
-
-
-
-
t
× 33
AD h
t
t
R Dd2
D QMd2
h
h
t
DAh
EP9307
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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