EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 15

IC ARM9 SOC ARM920T 272TFBGA

EP9307-CRZ

Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-CRZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1138

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
ALTERA
0
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/IRZ
Manufacturer:
ALTERA
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Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Memory Interface
Figure 2
values for the timings of each of the SDRAM modes.
SDRAM Load Mode Register Cycle
DS667PP3
SDCLK high time
SDCLK low time
SDCLK rise/fall time
Signal delay from SDCLK rising edge time
Signal hold from SDCLK rising edge time
DQMn delay from SDCLK rising edge time
DQMn hold from SDCLK rising edge time
DA valid setup to SDCLK rising edge time
DA valid hold from SDCLK rising edge time
SDWEn
SDCLK
SDCSn
DQMn
RASn
CASn
AD
DA
through
Figure 5
t
clkrf
define the timings associated with all phases of the SDRAM. The following table contains the
Parameter
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
t
d
Copyright 2004 Cirrus Logic (All Rights Reserved)
OP-Code
t
h
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Symbol
t
t
clk_high
clk_low
t
t
t
t
t
DQd
DQh
DAh
clkrf
DAs
t
t
d
h
t
Min
clk_low
-
-
-
-
-
-
-
-
-
(t
(t
HCLK
HCLK
Typ
t
3
8
4
6
6
2
2
clk_high
)/2
)/2
Max
-
-
-
-
-
-
-
-
-
EP9307
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
15

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