EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 42

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Pin List
The following Thin-profile Fine-pitch Ball Grid Array (TFBGA) ball assignment table is sorted in order of ball.
42
Ball
A10
A12
A13
A14
A15
A16
A17
B10
B12
B13
B14
B15
B16
B17
A11
B11
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
SDCLKEN
EGPIO[15]
ADC_VDD
MIIRXD[3]
MIIRXD[1]
MIITXD[1]
MIITXD[2]
HGPIO[2]
HGPIO[3]
HGPIO[5]
FGPIO[7]
FGPIO[0]
FGPIO[5]
USBm[2]
RXDVAL
USBp[2]
Signal
RXCLK
ARSTn
CSn[1]
CSn[7]
DA[31]
DA[29]
DA[27]
WAITn
AD[25]
CSn[2]
CSn[6]
AD[20]
DA[30]
AD[18]
AD[17]
AD[23]
DA[26]
CSn[3]
DA[25]
AD[24]
AD[19]
TXEN
ASDI
WRn
CRS
RDn
Ball
G12
G13
E10
E11
E12
E13
E14
E15
E16
E17
F10
F11
F12
F13
F14
F15
F16
F17
G1
G2
G3
G4
G5
G6
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
Copyright 2004 Cirrus Logic (All Rights Reserved)
ADC_GND
MIIRXD[0]
SDCSn[2]
SDCSn[1]
SDCSn[0]
EGPIO[2]
EGPIO[4]
EGPIO[3]
EGPIO[7]
EGPIO[5]
EGPIO[6]
EGPIO[9]
DQMn[3]
DQMn[0]
SDWEN
Signal
TXERR
DA[22]
DA[15]
AD[21]
DA[17]
DA[21]
AD[22]
AD[3]
RASn
AD[5]
CASn
vddc
vddc
vddr
vddr
vddr
sXm
gndr
gndr
gndr
gndr
sYm
vddr
gndr
gndr
sXp
sYp
Ball
K10
K12
K13
K14
K15
K16
K17
L12
L13
L14
L15
L16
L17
J10
J12
J13
J14
J15
J16
J17
M1
M2
M3
M4
M5
M6
M7
M8
K1
K2
K3
K4
K5
K6
K8
K9
L1
L2
L3
L4
L5
L6
PLL_GND
PLL_VDD
DQMn[1]
DQMn[2]
BRIGHT
ROW[7]
ROW[5]
Signal
BLANK
XTALO
COL[5]
COL[6]
CSn[0]
COL[3]
DA[12]
DA[10]
COL[4]
COL[2]
COL[1]
COL[0]
DA[11]
XTALI
AD[4]
DA[9]
AD[2]
AD[1]
DA[8]
AD[0]
P[17]
gndc
vddc
gndr
gndc
gndc
gndc
vddc
gndr
gndr
gndr
gndr
vddc
vddr
vddr
Ball
R10
R12
R13
R14
R15
R16
R17
P10
P12
P13
P14
P15
P16
P17
R11
P11
P1
P2
P3
P4
P5
P6
P7
P8
P9
R1
R2
R3
R4
R5
R6
R7
R8
R9
T1
T2
T3
T4
T5
T6
T7
T8
V_CSYNC
PWMOUT
GGPIO[2]
SSPTX[1]
ABITCLK
USBm[0]
BOOT[1]
BOOT[0]
USBp[0]
Signal
GRLED
RDLED
HSYNC
ASYNC
SPCLK
EEDAT
RXD[1]
RXD[2]
AD[15]
AD[13]
AD[12]
AD[14]
AD[11]
DA[2]
AD[8]
DA[4]
DA[1]
DTRn
DA[7]
AD[9]
P[10]
P[11]
TCK
P[3]
P[9]
P[6]
P[5]
P[0]
P[7]
P[2]
TDI
NC
NC
DS667PP3