EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 25

IC ARM9 SOC ARM920T 272TFBGA

EP9307-CRZ

Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-CRZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1138

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
ALTERA
0
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/IRZ
Manufacturer:
ALTERA
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Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Static Memory Burst Read Cycle
DS667PP3
CSn assert to Address 1 transition time
Address 2 assert time
AD hold from CSn deassert time
CSn assert time
CSn to RDn assert delay time
RDn assert time
CSn to DQMn assert delay time
DQMn assert time
DA to AD setup time
DA to CSn setup time
AD transition to DA transition hold time
CSn deassert to DA transition hold time
DQMn
WAIT
WRn
Note:
CSn
RDn
AD
DA
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
t
DQMd
t
Parameter
RDd
t
Figure 12. Static Memory Burst Read Cycle Timing Measurement
ADd1
Copyright 2004 Cirrus Logic (All Rights Reserved)
t
DAs1
Symbol
t
t
DQMpw
t
t
t
t
t
t
t
t
DQMd
t
CSpw
t
RDpw
ADd1
ADd2
DAs1
DAs2
DAh1
DAh2
ADh
RDd
t
DAh1
t
ADd2
Min
t
DAs1
0
-
-
-
-
-
-
-
-
-
-
-
ARM9 SOC with Ethernet, USB, Display and Touchscreen
t
t
t
HCLK
HCLK
HCLK
t
t
DQMpw
t
t
CSpw
RDpw
DAh1
t
ADd2
× ((WST1 + 1) + 4(WST2 + 1))
× ((WST1 + 1) + 4(WST2 + 1))
× ((WST1 + 1) + 4(WST2 + 1))
t
t
HCLK
HCLK
t
DAs1
t
t
HCLK
× (WST1 + 1)
× (WST2 + 1)
HCLK
Typ
0
4
6
0
0
+ 6
× 2
t
DAh1
t
ADh
t
DAs2
Max
-
-
-
-
-
-
-
-
-
-
-
-
t
DAh2
EP9307
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25

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