C8051F413-GM Silicon Laboratories Inc, C8051F413-GM Datasheet - Page 179

• Manufacturer Part Number: C8051F413-GM
• Description: IC 8051 MCU 16K FLASH 28QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F41xr

Specifications of C8051F413-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 20
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 20x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 2-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1454 - ADAPTER PROGRAM TOOLSTICK F411336-1317 - KIT EVAL FOR C8051F411336-1314 - KIT DEV FOR C8051F41X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1311

ning of each series of consecutive reads. Software must check if the smaRTClock Interface is busy prior to
reading RTC0DAT. Autoread is enabled by setting AUTORD (RTC0ADR.6) to logic 1.
20.1.4. RTC0ADR Autoincrement Feature
For ease of reading and writing the 48-bit CAPTURE and ALARM values, RTC0ADR automatically incre-
ments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting
an alarm or reading the current smaRTClock timer value.
smaRTClock
0x00 - 0x05
0x08–0x0D
Address
0x0E
0x06
0x07
0x0F
smaRTClock
CAPTUREn smaRTClock Capture
RAMADDR
RAMDATA
RTC0XCN
Register
RTC0CN
ALARMn
Table 20.1. smaRTClock Internal Registers
Registers
smaRTClock Control
Register
smaRTClock Oscillator
Control Register
smaRTClock Alarm
Registers
smaRTClock Backup RAM
Indirect Address Register
smaRTClock Backup RAM
Indirect Data Register
Register Name
Rev. 1.1
Six Registers used for setting the 47-bit
smaRTClock timer or reading its current
value. The LSB of CAPTURE0 is not used.
Controls the operation of the smaRTClock
State Machine.
Controls the operation of the smaRTClock
Oscillator.
Six registers used to set or read the 47-bit
smaRTClock alarm value. The LSB of
ALARM0 is not used.
Used as an index to the 64 byte smaRTClock
backup RAM.
Used to read or write the byte pointed to by
RAMADDR.
C8051F410/1/2/3
Description
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