ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet - Page 178

• Manufacturer Part Number: ATMEGA169L-8MI
• Description: IC MCU AVR 16K LV 8MHZ IND 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169L-4MI; ATMEGA169L-4MI

Universal Serial
Interface – USI
Overview
178
ATmega169V/L
The Universal Serial Interface, or USI, provides the basic hardware resources needed
for serial communication. Combined with a minimum of control software, the USI allows
significantly higher transfer rates and uses less code space than solutions based on
software only. Interrupts are included to minimize the processor load. The main features
of the USI are:
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•
•
•
•
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A simplified block diagram of the USI is shown on Figure 75. For the actual placement of
I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible I/O Registers, includ-
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the “USI Register Descriptions” on page 184.
Figure 75. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming
and outgoing data. The register has no buffering so the data must be read as quickly as
possible to ensure that no data is lost. The most significant bit is connected to one of two
output pins depending of the wire mode configuration. A transparent latch is inserted
between the Serial Register Output and output pin, which delays the change of data out-
put to the opposite clock edge of the data input sampling. The serial input is always
sampled from the Data Input (DI) pin independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an
overflow interrupt. Both the Serial Register and the counter are clocked simultaneously
by the same clock source. This allows the counter to count the number of bits received
or transmitted and generate an interrupt when the transfer is complete. Note that when
an external clock source is selected the counter counts both clock edges. In this case
the counter counts the number of edges, and not the number of bits. The clock can be
selected from three different sources: The USCK pin, Timer/Counter0 Compare Match
or from software.
Two-wire Synchronous Data Transfer (Master or Slave, f
Three-wire Synchronous Data Transfer (Master or Slave f
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
USIDR
USISR
USICR
2
4-bit Counter
3
2
1
0
3
2
1
0
D Q
LE
[1]
TIM0 COMP
0
1
Two-wire Clock
Control Unit
SCLmax
SCKmax
= f
CLOCK
HOLD
= f
CK
CK
/16)
/4)
DO
DI/SDA
USCK/SCL
2514H–AVR–05/03
(Output only)
(Input/Open Drain)
(Input/Open Drain)