ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet - Page 281

• Manufacturer Part Number: ATMEGA169L-8MI
• Description: IC MCU AVR 16K LV 8MHZ IND 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169L-4MI; ATMEGA169L-4MI

Serial Programming
Algorithm
Data Polling Flash
2514H–AVR–05/03
When writing serial data to the ATmega169, data is clocked on the rising edge of SCK.
When reading data from the ATmega169, data is clocked on the falling edge of SCK.
See Figure 128 for timing details.
To program and verify the ATmega169 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in Table 130):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Program-
3. The serial programming instructions will not work if the communication is out of
4. The Flash is programmed one page at a time. The page size is found in Table
5. The EEPROM array is programmed one byte at a time by supplying the address
6. Any memory location can be verified by using the Read instruction which returns
7. At the end of the programming session, RESET can be set high to commence
8. Power-off sequence (if needed):
When a page is being programmed into the Flash, reading an address location within
the page being programmed will give the value 0xFF. At the time the device is ready for
a new page, the programmed value will read correctly. This is used to determine when
the next page can be written. Note that the entire page is written simultaneously and any
address within the page can be used for polling. Data polling of the Flash will not work
for the value 0xFF, so when programming this value, the user will have to wait for at
least t
0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be
skipped. See Table 129 for t
Apply power between V
some systems, the programmer can not guarantee that SCK is held low during
power-up. In this case, RESET must be given a positive pulse of at least two
CPU clock cycles duration after SCK has been set to “0”.
ming Enable serial instruction to pin MOSI.
synchronization. When in sync. the second byte (0x53), will echo back when
issuing the third byte of the Programming Enable instruction. Whether the echo
is correct or not, all four bytes of the instruction must be transmitted. If the 0x53
did not echo back, give RESET a positive pulse and issue a new Programming
Enable command.
125 on page 271. The memory page is loaded one byte at a time by supplying
the 6 LSB of the address and data together with the Load Program Memory
Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program
Memory Page is stored by loading the Write Program Memory Page instruction
with the 8 MSB of the address. If polling is not used, the user must wait at least
t
programming interface before the Flash write operation completes can result in
incorrect programming.
and data together with the appropriate Write instruction. An EEPROM memory
location is first automatically erased before new data is written. If polling is not
used, the user must wait at least t
Table 129.) In a chip erased device, no 0xFFs in the data file(s) need to be
programmed.
the content at the selected address at serial output MISO.
normal operation.
Set RESET to “1”.
Turn V
WD_FLASH
WD_FLASH
CC
power off.
before issuing the next page. (See Table 129.) Accessing the serial
before programming the next page. As a chip-erased device contains
CC
WD_FLASH
and GND while RESET and SCK are set to “0”. In
value.
WD_EEPROM
before issuing the next byte. (See
ATmega169V/L
281