ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet - Page 261

• Manufacturer Part Number: ATMEGA169L-8MI
• Description: IC MCU AVR 16K LV 8MHZ IND 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169L-4MI; ATMEGA169L-4MI

Setting the Boot Loader Lock
Bits by SPM
EEPROM Write Prevents
Writing to SPMCSR
Reading the Fuse and Lock
Bits from Software
2514H–AVR–05/03
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only
accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot
Loader section from any software update by the MCU.
See Table 109 and Table 110 for how the different settings of the Boot Loader bits affect
the Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed
if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it
is recommended to load the Z-pointer with 0x0001 (same as used for reading the lO
bits). For future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”
when writing the Lock bits. When programming the Lock bits the entire Flash can be
read during the operation.
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEWE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR.
When an LPM instruction is executed within three CPU cycles after the BLBSET and
SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destina-
tion register. The BLBSET and SPMEN bits will auto-clear upon completion of reading
the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM
instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared,
LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for
reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and
set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value
of the Fuse Low byte (FLB) will be loaded in the destination register as shown below.
Refer to Table 120 on page 268 for a detailed description and mapping of the Fuse Low
byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination
register as shown below. Refer to Table 119 on page 268 for detailed description and
mapping of the Fuse High byte.
Bit
R0
Bit
Rd
Bit
Rd
Bit
Rd
FHB7
FLB7
7
1
7
–
7
7
FHB6
FLB6
6
1
6
–
6
6
BLB12
BLB12
FHB5
FLB5
5
5
5
5
BLB11
BLB11
FLB4
FHB4
4
4
4
4
BLB02
BLB02
FLB3
FHB3
3
3
3
3
BLB01
BLB01
FHB2
FLB2
2
2
2
2
ATmega169V/L
FHB1
FLB1
LB2
1
1
1
1
1
FHB0
FLB0
LB1
0
1
0
0
0
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