P89LPC931FDH,112 NXP Semiconductors, P89LPC931FDH,112 Datasheet - Page 12

IC 80C51 MCU FLASH 8K 28-TSSOP

P89LPC931FDH,112

Manufacturer Part Number
P89LPC931FDH,112
Description
IC 80C51 MCU FLASH 8K 28-TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC931FDH,112

Core Processor
8051
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSSOP
Processor Series
P89LPC9x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
26
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 45 C
For Use With
622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
568-1284-5
935273877112
P89LPC931FDH
P89LPC931FDH,129
P89LPC931FDH-S
Table 4:
* indicates SFRs that are bit addressable.
Name
ACC*
AUXR1
B*
BRGR0
BRGR1
BRGCON
CMP1
CMP2
DIVM
DPTR
FMADRH
FMADRL
FMCON
FMDATA
I2ADR
I2CON*
I2DAT
DPH
DPL
[2]
[2]
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Special function registers
Description
Accumulator
Auxiliary function register
B register
Baud rate generator rate
LOW
Baud rate generator rate
HIGH
Baud rate generator control
Comparator 1 control register
Comparator 2 control register
CPU clock divide-by-M
control
Data pointer (2 bytes)
Data pointer HIGH
Data pointer LOW
Program Flash address HIGH
Program Flash address LOW
Program Flash Control
(Read)
Program Flash Control
(Write)
Program Flash data
I
I
I
2
2
2
C slave address register
C control register
C data register
Bit address
Bit address
Bit address
SFR
addr.
BEH
BFH
BDH
ACH
ADH
DBH
D8H
DAH
E0H
A2H
F0H
95H
83H
82H
E7H
E6H
E4H
E5H
Bit functions and addresses
FMCMD.
I2ADR.6
CLKLP
BUSY
MSB
DF
E7
F7
7
-
-
-
-
-
FMCMD.
I2ADR.5
EBRR
I2EN
DE
E6
F6
6
-
-
-
-
-
FMCMD.
I2ADR.4
ENT1
CE1
CE2
STA
DD
E5
F5
5
-
-
-
FMCMD.
I2ADR.3
ENT0
STO
CP1
CP2
DC
E4
F4
4
-
-
-
FMCMD.
I2ADR.2
SRST
CN1
CN2
HVA
DB
E3
F3
SI
3
-
-
FMCMD.
I2ADR.1
OE1
OE2
HVE
DA
AA
E2
F2
0
2
-
-
FMCMD.
I2ADR.0
SBRGS
CO1
CO2
SV
E1
F1
D9
1
-
-
FMCMD.
BRGEN
CRSEL
CMF1
CMF2
LSB
DPS
GC
E0
D8
F0
OI
0
Reset value
Hex
00
00
00
00
00
00
00
00
00
00
00
00
00
70
00
00
00
[1]
[6]
[1]
[1]
Binary
00000000
000000x0
00000000
00000000
00000000
xxxxxx00
xx000000
xx000000
00000000
00000000
00000000
00000000
00000000
01110000
00000000
00000000
x00000x0

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