ST7FLITE09Y0B6 STMicroelectronics, ST7FLITE09Y0B6 Datasheet
ST7FLITE09Y0B6
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ST7FLITE09Y0B6 Summary of contents
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Flash memory, data EEPROM, ADC, timers, SPI Memories ■ – 1.5 Kbytes single voltage Flash Pro- gram memory with read-out protection, In-Cir- cuit and In-Application Programming (ICP and IAP write/erase cycles guaranteed, data retention: 20 years ...
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ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 DESCRIPTION . . . . . . . . ...
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I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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To obtain the most recent version of this datasheet, please check at www.st.com Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 121. Table of Contents 4/124 1 ...
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DESCRIPTION The ST7LITE0x and (ST7LITESx) are members of the ST7 microcon- troller family. All ST7 devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. The ST7LITE0x and ST7SUPERLITE feature FLASH memory with ...
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ST7LITE0xY0, ST7LITESxY0 2 PIN DESCRIPTION Figure 2. 20-Pin QFN Package Pinout MISO/AIN2/PB2 SCK/AIN1/PB1 Figure 3. 16-Pin SO and DIP Package Pinout k SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 6/124 RESET ...
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PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Type input output supply In/Output level: C= CMOS 0.15V C = CMOS 0.3V T Output level 20mA high sink (on N-buffer only) Port and control ...
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ST7LITE0xY0, ST7LITESxY0 Pin n° Pin Name 15 14 PA2/ATPWM0 I PA1 I PA0/LTIC I/O C Note: In the interrupt input column, “ei umn (wpu) is merged with the interrupt column (int), then the I/O ...
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REGISTER & MEMORY MAP As shown in Figure 4 and Figure pable of addressing 64K bytes of memories and I/ O registers. The available memory locations consist 128 bytes of register locations, 128 bytes of RAM, ...
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ST7LITE0xY0, ST7LITESxY0 REGISTER AND MEMORY MAP (Cont’d) Figure 5. Memory Map (ST7SUPERLITE) 0000h 007Fh 0080h 00FFh 0100h FBFFh FC00h FFDFh FFE0h Interrupt & Reset Vectors FFFFh 10/124 1 0080h HW Registers (see Table 2) 00BFh RAM 00C0h (128 Bytes) 00FFh ...
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REGISTER AND MEMORY MAP (Cont’d) Legend: x=undefined, R/W=read/write Table 2. Hardware Register Map Register Address Block 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h to 000Ah 000Bh LITE LTCSR 000Ch TIMER ...
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ST7LITE0xY0, ST7LITESxY0 Register Address Block 003Ah SI SICSR 003Bh to 007Fh Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead ...
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FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices can ...
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ST7LITE0xY0, ST7LITESxY0 FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC interface ICP needs a minimum of 4 and pins to be connected to the programming tool. These pins are: – RESET: device reset – device power supply ...
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FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a pro- tection ...
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ST7LITE0xY0, ST7LITESxY0 5 DATA EEPROM 5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 7. EEPROM ...
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DATA EEPROM (Cont’d) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 8 describes these different memory access modes. Read Operation ...
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ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 2 Figure 9. Data E PROM Write Operation ⇓ Row / Byte ⇒ ROW DEFINITION Byte 1 Byte 2 Writing data latches E2LAT bit Set by USER application E2PGM bit Note programming cycle ...
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DATA EEPROM (Cont’d) 5.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler or when the microcontroller enters Active Halt mode.The DATA EEPROM will immediately enter ...
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ST7LITE0xY0, ST7LITESxY0 DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- SR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access ...
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CENTRAL PROCESSING UNIT 6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main addressing modes ...
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ST7LITE0xY0, ST7LITESxY0 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just ...
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CPU REGISTERS (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 00 FFh SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location ...
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ST7LITE0xY0, ST7LITESxY0 7 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main ...
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Figure 13. PLL Output Frequency Timing Diagram LOCKED bit set 4/8 x input freq. t LOCK t STARTUP When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay ...
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ST7LITE0xY0, ST7LITESxY0 SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d) Figure 14. Clock Management Block Diagram CR7 CR6 CR5 Tunable 1% RC Oscillator /2 DIVIDER CLKIN f OSC /32 DIVIDER 7 26/124 1 CR4 CR3 CR2 CR1 CR0 PLL 1MHz -> 8MHz ...
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RESET SEQUENCE MANAGER (RSM) 7.4.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ Note: A reset can ...
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ST7LITE0xY0, ST7LITESxY0 RESET SEQUENCE MANAGER (Cont’d) 7.4.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R ON This pull-up has no fixed value but varies in ac- cordance with the input ...
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INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The ...
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ST7LITE0xY0, ST7LITESxY0 INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 6. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 Not used 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ei2 ...
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INTERRUPTS (Cont’d) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 IS21 IS20 IS11 Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table Bit 5:4 ...
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ST7LITE0xY0, ST7LITESxY0 8.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Volt- age Detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following ...
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Figure 20. Reset and Supply Management Block Diagram RESET SEQUENCE RESET MANAGER (RSM WATCHDOG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT SICSR LOC KED 7 LOW VOLTAGE DETECTOR (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) ST7LITE0xY0, ...
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ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply voltage (V ). The V AVD IT-(AVD) ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.3 Low Power Modes Mode Description No effect on SI. AVD interrupts cause the WAIT device to exit from Wait mode. The SICSR register is frozen. HALT The AVD remains active but the AVD inter- rupt ...
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ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0000 0x00 (0xh) 7 LOCK Bit 7:4 = Reserved, must be kept cleared. Bit 3 = LOCKED ...
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POWER SAVING MODES 9.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 22): SLOW, WAIT (SLOW WAIT), AC- ...
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ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. ...
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POWER SAVING MODES (Cont’d) 9.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ...
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ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d) 9.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when active halt mode is disa- bled. The MCU can exit ...
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POWER SAVING MODES (Cont’d) 9.4.2.1 HALT Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O ...
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ST7LITE0xY0, ST7LITESxY0 10 I/O PORTS 10.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. ...
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RIM instruc- tion (in cases where a pin level change could occur) Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR ...
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ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) Figure 29. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION Table ...
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I/O PORTS (Cont’d) Table 10. I/O Port Configurations PAD PAD PAD Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function ...
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ST7LITE0xY0, ST7LITESxY0 I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used ...
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I/O PORTS (Cont’d) Table 12. I/O Port Register Map and Reset Values Address Register Label (Hex.) PADR MSB 0000h Reset Value PADDR MSB 0001h Reset Value PAOR MSB 0002h Reset Value PBDR MSB 0003h Reset Value PBDDR MSB 0004h Reset ...
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ST7LITE0xY0, ST7LITESxY0 11 ON-CHIP PERIPHERALS 11.1 LITE TIMER (LT) 11.1.1 Introduction The Lite Timer can be used for general-purpose timing functions based on a free-running 8-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and ...
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LITE TIMER (Cont’d) 11.1.3 Functional Description The value of the 8-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter overflow event occurs when the counter ...
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ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) Figure 32. Watchdog Timing Diagram f WDG WDGD BIT INTERNAL WATCHDOG RESET 50/124 1 HARDWARE CLEARS WDGD BIT t WDG (2ms @ 8 MHz f ) OSC SOFTWARE SETS WDGD BIT WATCHDOG RESET ...
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LITE TIMER (Cont’d) Input Capture The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and ...
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ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d) 11.1.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR) Read / Write Reset Value: 0x00 0000 (x0h) 7 ICIE ICF TB TBIE TBF Bit 7 = ICIE Interrupt Enable This bit is set and cleared by ...
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AUTORELOAD TIMER (AT) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for gen- eral-purpose timing functions based on a free- running 12-bit upcounter with a PWM output chan- nel. 11.2.2 Main Features 12-bit upcounter with ...
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.3 Functional Description PWM Mode This mode allows a Pulse Width Modulated sig- nals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled ...
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AUTORELOAD TIMER (Cont’d) Figure 36. PWM Signal Example f COUNTER COUNTER FFDh DCR0=FFEh Output Compare Mode To use this function, the OE bit must be 0, other- wise the compare is done with the shadow register instead of the ...
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATC- SR) Read / Write Reset Value: 0000 0000 (00h CK1 CK0 Bit 7:5 = Reserved, must be kept cleared. Bit 4:3 = ...
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AUTORELOAD TIMER (Cont’d) AUTO RELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h ATR11 ATR10 ATR9 AUTO RELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h) 7 ATR7 ATR6 ATR5 ...
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ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h Table 14. Register Map and Reset Values Address Register Label (Hex.) ATCSR 0D Reset Value CNTRH 0E ...
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SERIAL PERIPHERAL INTERFACE (SPI) 11.3.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not ...
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 38. The MOSI pins are connected together and the MISO pins are connected together. ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 41). Note: The idle state of SCK must correspond to the polarity selected ...
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5 Error Flags 11.3.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 43). The master device selects the individual slave de- vices by ...
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.3.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt ...
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ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 16. SPI Register Map and Reset Values Address Register Label (Hex.) SPIDR MSB 31 Reset Value SPICR SPIE 32 Reset Value SPICSR SPIF 33 Reset Value SPE SPR2 MSTR ...
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ST7LITE0xY0, ST7LITESxY0 11.4 8-BIT A/D CONVERTER (ADC) 11.4.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input ...
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Figure 44. ADC Block Diagram f CPU DIV 2 7 EOC SPEED ADON AIN0 AIN1 ANALOG MUX AINx (ADCAMP Register) DIV SLOW bit 0 0 CH2 CH1 3 HOLD CONTROL R ADC ...
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ST7LITE0xY0, ST7LITESxY0 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.4.3.3 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the ...
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A/D CONVERTER (ADC) (Cont’d) 11.4.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 0 Bit 7 = EOC Conversion Complete This bit is set by hardware cleared by soft- ...
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ST7LITE0xY0, ST7LITESxY0 Table 17. ADC Register Map and Reset Values Address Register Label (Hex.) ADCCSR EOC 34h Reset Value ADCDR 35h Reset Value ADCAMP 36h Reset Value 74/124 SPEED ADON ...
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INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative ...
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ST7LITE0xY0, ST7LITESxY0 ST7 ADDRESSING MODES (cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt ...
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ST7 ADDRESSING MODES (cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST7LITE0xY0, ST7LITESxY0 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations ...
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INSTRUCTION GROUPS (cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL ...
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ST7LITE0xY0, ST7LITESxY0 INSTRUCTION GROUPS (cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF ...
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ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...
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ST7LITE0xY0, ST7LITESxY0 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage ...
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OPERATING CONDITIONS 13.3.1 General Operating Conditions: Suffix 6 Devices T = -40 to +85°C unless otherwise specified. A Symbol Parameter V Supply voltage DD External clock frequency on f CLKIN CLKIN pin Figure 48. f Maximum Operating Frequency Versus ...
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ST7LITE0xY0, ST7LITESxY0 13.3.2 Operating Conditions with Low Voltage Detector (LVD -40 to 85°C, unless otherwise specified A Symbol Parameter Reset release threshold V IT+ (LVD) (V rise) DD Reset generation threshold V (LVD) IT- (V fall ...
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Internal RC Oscillator and PLL The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter V Internal RC Oscillator operating voltage DD(RC PLL operating voltage DD(x4PLL) V ...
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ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) 13.3.4.2 Devices with ‘”6” order code suffix (tested for T Symbol Parameter Internal RC oscillator fre quency Accuracy of Internal RC ACC oscillator when calibrated RC with RCCR=RCCR1 RC oscillator current con- ...
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OPERATING CONDITIONS (Cont’d) Figure 49. RC Osc Freq vs V (Calibrated with RCCR1 25°C) 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 2.4 2.6 2.8 3 3.2 VDD (V) Figure 50. RC Osc Freq vs ...
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ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) Figure 54. PLLx4 Output vs CLKIN frequency 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 1.5 2 External Input Clock Frequency (MHz) Note /2*PLL4 OSC CLKIN 88/124 1 Figure 55. PLLx8 Output ...
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SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- 13.4.1 Supply Current T = -40 ...
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ST7LITE0xY0, ST7LITESxY0 SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 58. Typical I in WAIT vs 8MHz 2.0 4MHz 1.5 1MHz 1.0 0.5 0.0 2.4 2.7 3.7 Vdd (V) Figure 59. Typical I in SLOW-WAIT vs 250kHz 0.70 125kHz ...
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CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 13.5.2 External Clock Source Symbol Parameter ...
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ST7LITE0xY0, ST7LITESxY0 13.6 MEMORY CHARACTERISTICS T = -40°C to 105°C, unless otherwise specified A 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Program Memory Symbol Parameter V Operating voltage for Flash write/erase DD Programming ...
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EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling two -+LEDs through I/O ports), the product ...
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... Static latch-up class Note: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V 1) hys hysteresis I Input leakage current ...
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ST7LITE0xY0, ST7LITESxY0 I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 65) ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 64. Typical 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0. lio (mA) Figure 65. Typical 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 ...
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ST7LITE0xY0, ST7LITESxY0 Figure 69. Typical 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 lio(mA) Figure 70. Typical 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 lio (mA) Figure ...
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Figure 74. Typical V vs 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 2.4 3 VDD (V) Figure 75. Typical 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 4 VDD (high-sink ...
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ST7LITE0xY0, ST7LITESxY0 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40°C to 105°C, unless otherwise specified A Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 76. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01µF Figure 77. RESET pin protection when LVD is disabled. USER EXTERNAL RESET CIRCUIT 0.01µF Required Note 1: – The reset network protects the ...
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ST7LITE0xY0, ST7LITESxY0 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK = SPI clock frequency 1/t c(SCK) t r(SCK) ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 79. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t MOSI INPUT Figure 80. SPI Master Timing ...
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ST7LITE0xY0, ST7LITESxY0 13.11 8-BIT ADC CHARACTERISTICS T = -40°C to 85°C, unless otherwise specified A Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input resistor AIN C Internal sample and hold capacitor ADC t ...
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ADC CHARACTERISTICS (Cont’d) Figure 82. R max AIN ADC (pF) PARASITIC Notes represents the capacitance of the PCB (dependent on soldering and ...
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ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) ADC Accuracy with V =5. -40°C to 85°C, unless otherwise specified A Symbol Parameter E Total unadjusted error Offset error Gain Error G E Differential linearity ...
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ADC CHARACTERISTICS (Cont’d) Figure 84. ADC Accuracy Characteristics with Amplifier disabled Digital Result ADCDR 255 V – 254 DDA 1LSB = ---------------------------------------- - IDEAL 256 253 LSB ...
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ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Vout (ADC input) Vmax Vmin 0V 0V Symbol Parameter V Amplifier operating voltage DD(AMP) V Amplifier input voltage IN V Amplifier offset voltage OFFSET V Step size for monotonicity STEP Output Voltage Response Linearity Gain ...
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PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level in- terconnect. The category of second Level Inter- connect is marked on the package and on the ...
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ST7LITE0xY0, ST7LITESxY0 Figure 87. 16-Pin Plastic Dual In-Line Package, 300-mil Width Figure 88. 16-Pin Plastic Small Outline Package, 150-mil Width 110/124 ...
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THERMAL CHARACTERISTICS Symbol Package thermal resistance R thJA (junction to ambient) T Maximum junction temperature Jmax P Power dissipation Dmax Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from ...
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ST7LITE0xY0, ST7LITESxY0 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (FASTROM). ST7PLITE0x and ST7PLITES2/S5 devices are Factory Advanced Service Technique ROM (FAS- TROM) ...
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OPTION BYTES (Cont’d) OPTION BYTE 1 Bit 7 = PLLx4x8 PLL Factor selection. 0: PLLx4 1: PLLx8 Bit 6 = PLLOFF PLL disabled 0: PLL enabled 1: PLL disabled (by-passed) Bit 5 = Reserved, must always be 1. Table 21. ...
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... FFh. The selected op- tions are communicated to STMicroelectronics us- ing the correctly completed OPTION LIST append- ed. 114/124 Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. ...
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Figure 89. Ordering information scheme Example: Family ST7 Microcontroller Family Memory type F: Flash P: FASTROM Sub-family LITES2, LITES5, LITE02, LITE05 or LITE09 No. of pins Memory size (LITESx versions) or 1.5K (LITE0x versions) ...
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... Reference/FASTROM Code *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. ...
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... DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- clude a complete range of hardware systems and software tools from STMicroelectronics and third- party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers. ...
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ST7LITE0xY0, ST7LITESxY0 15.4 ST7 APPLICATION NOTES Table 24. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI ...
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Table 24. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK ...
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ST7LITE0xY0, ST7LITESxY0 Table 24. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- AN1179 GRAMMING) AN1446 ...
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KNOWN LIMITATIONS 16.1 Execution of BTJX Instruction Description Executing a BTJx instruction jumps to a random address in the following conditions: the jump goes to a lower address (jump backward) and the test is performed on a data located ...
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ST7LITE0xY0, ST7LITESxY0 17 REVISION HISTORY Table 25. Revision History Date Revision Revision number incremented from 2.5 to 3.0 due to Internal Document Management Sys- tem change Changed all references of ADCDAT to ADCDR Added EMU3 Emulator Programming Capability in Clarification ...
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Removed QFN20 pinout and mechanical data. Modified text in External Interrupt Function section in Modified 09-Oct-06 5 Added “External Clock Source” on page 91 and Modified description of CNTR[11:0] bits in Updated option list on Changed Title of the document ...
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... ST7LITE0xY0, ST7LITESxY0 Notes: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...