ST7FLITE09Y0B6 STMicroelectronics, ST7FLITE09Y0B6 Datasheet - Page 20

MCU 8BIT 1.5KB FLASH 128KB 16DIP

ST7FLITE09Y0B6

Manufacturer Part Number
ST7FLITE09Y0B6
Description
MCU 8BIT 1.5KB FLASH 128KB 16DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITE09Y0B6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-DIP (0.300", 7.62mm)
Processor Series
ST7FLITE0x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FLIT0-IND/USB, ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
497-6250 - BOARD RGB COLOR CTRL STP04CM596497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5632-5

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ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-
SR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: If the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed.
Table 4. DATA EEPROM Register Map and Reset Values
20/124
1
Address
7
0
(Hex.)
0030h
0
EECSR
Reset Value
Register
0
Label
0
0
7
0
0
E2LAT E2PGM
6
0
0
5
0
4
0
3
0
2
0
E2LAT
1
0
E2PGM
0
0

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