ST7FLITE09Y0B6 STMicroelectronics, ST7FLITE09Y0B6 Datasheet - Page 122

• Manufacturer Part Number: ST7FLITE09Y0B6
• Description: MCU 8BIT 1.5KB FLASH 128KB 16DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE09Y0B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Processor Series: ST7FLITE0x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLIT0-IND/USB, ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-6250 - BOARD RGB COLOR CTRL STP04CM596497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5632-5

ST7LITE0xY0, ST7LITESxY0
17 REVISION HISTORY
Table 25. Revision History
122/124
21-July-06
27-Oct-04
Date
Revision
3
4
Revision number incremented from 2.5 to 3.0 due to Internal Document Management Sys-
tem change
Changed all references of ADCDAT to ADCDR
Added EMU3 Emulator Programming Capability in
Clarification of read-out protection
Altered note 1 for
Alteration of f
on page 90
Removed sentence relating to an effective change only after overflow for CK[1:0],
Added illegal opcode detection to page 1,
Clarification of Flash read-out protection,
f
Updated F
section 8.4.4 on page
the AVDF bit is set”
Socket Board development kit details added in
PWM Signal diagram corrected,
Corrected count of reserved bits between 003Bh to 007Fh,
Inserted note that RCCR0 and RCCR1 are erased if read-only flag is reset,
page 24
Added QFN20 package
Modified
Changed Read operation paragraph in
Modified note below
Modified note to
Added note on illegal opcode reset to
Added note 2 to EICR description on
Modified External Interrupt Function in
Changed text on input capture before
Modified text in
Added important note in
Changed note 1 in
Modified values in
Modified note 2 in
Added note on clock stability and frequency accuracy to
13.3.4.2 on page
113
Changed I
Added note in
Changed
101
Changed
Modified
Added ECOPACK information to
Modified
Modified
Modified
Updated option list on
Changed
Removed erratasheet section
Added
Revision History continued overleaf ...
PLL
value of 1MHz quoted as Typical instead of a Minimum in
(device works correctly without these components)
Section 16.4
section 2 on page 6
Figure 79
Figure 88 on page 110
Table 21 on page 112
section 15.2 on page 114
Figure 76 on page 101
section 13.10.1 on page 102
section 15.3 on page 117
S
SCK
value and note 2 in
CPU
Figure 62 on page 95
in
section 11.1.5 on page 51
section 7.1 on page 24
section 13.10.1 on page 102
86,
for SLOW and SLOW-WAIT modes in
section 13.2.3 on page 82
section 13.3.4.1 on page 85
section 13.2.2 on page 82
section 13.2 on page 82
(CPHA=1) and
and
Figure 9 on page 18
section 7.1 on page 24
36: Changed wording in AVDIE and AVDF bit descriptions to “...when
page 116
section 11.3.3.3 on page 62
section 16.5 on page 121
section 13.8.1 on page 95
and removed EMC protection circuitry in
Figure 36 on page 55
(A1 and A swapped in the diagram)
Description of changes
section 14 on page 109
Figure 80 on page 103
page 31
section 7.4.1 on page 27
section 11.1.4 on page 51
section 10.2.1 on page 42
(t
section 5.3 on page 17
su(SS),
section 4.5.1 on page 15
and modified
section 8.4 on page
removing references to RESET
and to OSC option bit in
to F
t
and
Table 24 on page 115
v(MO) and
CPU
Table 23
section 13.3.4.2 on page 86
/4 and F
section 13.3.4.1 on page
section 5.5 on page 19
Section 13.4.1
t
h(MO)
(t
Table 2 on page 11
v(MO) ,
section 14.3.5.2 on page 92
)
32,
CPU
t
section 12 on page 75
/2
h(MO)
Section 15.1
table and
)
Figure 77 on page
section 7.1 on
85,
Figure 59
page 56
on
section
page