ST7FLITE09Y0B6 STMicroelectronics, ST7FLITE09Y0B6 Datasheet - Page 72

• Manufacturer Part Number: ST7FLITE09Y0B6
• Description: MCU 8BIT 1.5KB FLASH 128KB 16DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE09Y0B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Processor Series: ST7FLITE0x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLIT0-IND/USB, ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-6250 - BOARD RGB COLOR CTRL STP04CM596497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5632-5

ST7LITE0xY0, ST7LITESxY0
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.4.3.3 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
to V
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (V
V
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
R
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.4.3.4 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in
■
■
■
While the ADC is on, these two phases are contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
11.4.3.5 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in
tions and to
72/124
1
SSA
AIN
Sample capacitor loading [duration: t
During this phase, the V
measured is loaded into the C
capacitor.
A/D conversion [duration: t
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the C
from the analog input pin to get the optimum
analog to digital conversion accuracy.
The total conversion time:
t
CONV =
DDA
is the maximum recommended impedance
(low-level voltage reference) then the con-
(high-level voltage reference) then the
t
SAMPLE
ADC
Figure 45
sample capacitor is disconnected
Section 11.4.6
AIN
+ t
Figure
HOLD
AIN
) is lower than or equal to
for the timings.
) is greater than or equal
AIN
45:
HOLD
input voltage to be
for the bit defini-
]
ADC
SAMPLE
sample
]
ADC Configuration
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
ADC Conversion
In the CSR register:
When a conversion is complete
A write to the ADCCSR register (with ADON set)
aborts the current conversion, resets the EOC bit
and starts a new conversion.
Figure 45. ADC Conversion Timings
11.4.4 Low Power Modes
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
11.4.5 Interrupts
None
WAIT
HALT
ADON
HOLD
CONTROL
– Select the CH[2:0] bits to assign the analog
– Set the ADON bit to enable the A/D converter
– The EOC bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
Mode
channel to be converted.
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
valid until the next conversion has ended.
t
SAMPLE
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilization time before ac-
curate conversions can be performed.
t
CONV
t
HOLD
EOC BIT SET
Description
ADCCSR WRITE
OPERATION