ST10F272Z2Q3 STMicroelectronics, ST10F272Z2Q3 Datasheet - Page 18

• Manufacturer Part Number: ST10F272Z2Q3
• Description: MCU 16BIT 256KB FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272Z2Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5579

Pin data
Table 2.
18/189
P4.0 –P4.7
WR/WRL
Symbol
READY/
READY
ALE
RD
Pin description (continued)
85-92
Pin
85
86
87
88
89
90
91
92
95
96
97
98
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. The input threshold is selectable (TTL or
CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open
drain drivers.
In case of an external bus configuration, Port 4 can be used to output the
segment address lines:
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
External memory read strobe. RD is activated for every external instruction or
data read access.
External memory write strobe. In WR-mode this pin is activated for every external
data write access. In WRL mode this pin is activated for low byte data write
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
Ready input. The active level is programmable. When the ready function is
enabled, the selected inactive level at this pin, during an external memory
access, will force the insertion of waitstate cycles until the pin returns to the
selected active level.
Address latch enable output. In case of use of external addressing or of
multiplexed mode, this signal is the latch command of the address lines.
A16
A17
A18
A19
A20
CAN2_RxD
SCL
A21
CAN1_RxD
CAN2_RxD
A22
CAN1_TxD
CAN2_TxD
A23
CAN2_TxD
SDA
Segment address line
Segment address line
Segment address line
Segment address line
CAN2: receive data input
I
CAN1: receive data input
CAN2: receive data input
CAN1: transmit data output
CAN2: transmit data output
CAN2: transmit data output
I
Segment address line
Segment address line
Segment address line
Most significant segment address line
2
2
C Interface: serial clock
C Interface: serial data
Function
ST10F272Z2