MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 31

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 41
5.5
The locations of on-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be
accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read or
written using word accesses only.
Table 10
order of the base address.
Freescale Semiconductor
provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals.
summarizes the base addresses for the set of peripherals on the 56F8006/56F8002 devices. Peripherals are listed in
Peripheral Memory-Mapped Registers
Programmable Gain Amplifier 0
Programmable Gain Amplifier 1
Power Management Controller
Computer Operating Properly
Programmable Interval Timer
Programmable Delay Block
System Integration Module
Table 10. Data Memory Peripheral Base Address Map Summary
On-Chip Clock Synthesis
Flash Memory Interface
Analog Comparator 0
Analog Comparator 1
Analog Comparator 2
Dual Channel Timer
Interrupt Controller
Real Timer Clock
PWM Module
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
GPIO Port F
Peripheral
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
ADCA
ADCB
SCI
SPI
I
2
C
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
OCCS
Prefix
ADCA
ADCB
CMP0
CMP1
CMP2
PGA0
PGA1
PWM
INTC
PMC
TMR
COP
PDB
RTC
SCI
SIM
SPI
PIT
I
FM
2
C
Base Address
X:0x00 F0C0
X:0x00 F1C0
X:0x00 F2C0
X:0x00 F0A0
X:0x00 F0E0
X:0x00 F1A0
X:0x00 F1E0
X:0x00 F2A0
X:0x00 F2E0
X:0x00 F000
X:0x00 F020
X:0x00 F040
X:0x00 F060
X:0x00 F080
X:0x00 F100
X:0x00 F120
X:0x00 F140
X:0x00 F160
X:0x00 F180
X:0x00 F200
X:0x00 F220
X:0x00 F240
X:0x00 F260
X:0x00 F280
X:0x00 F300
X:0x00 F320
X:0x00 F400
Memory Maps
31