MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 9

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3
The 56F8006/56F8002’s architecture is shown in
communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core.
Figure 3
(SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other
peripherals.
Freescale Semiconductor
shows the peripherals and control blocks connected to the IPBus bridge. Please see the system integration module
Architecture Block Diagram
Program Control Unit
HWS0
HWS1
FIRA
LA2
Manipulation
LA
PC
JTAG TAP
Enhanced
OnCE™
OMR
LC2
SR
LC
Unit
FISR
Bit-
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
Instruction
Decoder
Interrupt
Looping
Unit
Unit
Figure 2. 56800E Core Block Diagram
DSP56800E Core
Y
A2
B2
C2
D2
Figure 2
MAC and ALU
Generation
Address
C1
D1
(AGU)
A1
B1
Y1
Y0
X0
and
M01
Unit
N3
Figure
Multi-Bit Shifter
Arithmetic
Logic Unit
3.
(ALU)
Figure 2
Data
ALU1
A0
B0
C0
D0
illustrates how the 56800E system buses
R0
R1
SP
R2
R3
R4
R5
N
ALU2
CDBW
CDBR
XDB2
XAB1
XAB2
PDB
PAB
Interface
Program
Program
Memory
IPBus
Data/
RAM
Overview
9