MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet - Page 59

• Manufacturer Part Number: MC56F8002VWL
• Description: DSC 12K FLASH 32MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8002VWL

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 15x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Instruction Set Architecture: Dual Harvard
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 40
• Data Ram Size: 2 KB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8006DEMO, APMOTOR56F8000E
• Interface Type: LIN, I2C, SCI, SPI
• Minimum Operating Temperature: - 40 C
• For Use With: APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.13.3
Freescale Semiconductor
1
2
Pulse width of spikes that must be suppressed by the input filter
The master mode I
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
The maximum t
Bus free time between STOP and START condition
After this period, the first clock pulse is generated.
SCI receive
SCI receive
Set-up time for a repeated START condition
data pin
data pin
Hold time (repeated) START condition.
(Input)
(Input)
Inter-Integrated Circuit Interface (I
RXD
TXD
Data hold time for I
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
HIGH period of the SCL clock
HD; DAT
LOW period of the SCL clock
2
SCL Clock Frequency
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
Data set-up time
Characteristic
must be met only if the device does not stretch the LOW period (t
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3
2
C bus devices
Figure 29. RXD Pulse Width
Figure 30. TXD Pulse Width
Table 30. I
RXD
TXD
PW
PW
2
C Timing
Symbol
t
t
t
t
t
SU; STO
HD; STA
SU; STA
HD; DAT
SU; DAT
2
t
t
f
t
HIGH
LOW
SCL
BUF
t
C) Timing
SP
t
t
r
f
Minimum
250
N/A
4.0
4.7
4.0
4.7
4.0
4.7
0
—
—
Standard Mode
0
1
LOW
) of the SCL signal.
Maximum
3.45
1000
100
300
N/A
—
—
—
—
—
—
—
2
Specifications
Unit
MHz
ns
ns
ns
ns
s
s
s
s
s
s
s
59