DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 372
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 13 Serial Communication Interface (SCI)
Notes: 1. Only a 0 can be written to this bit, to clear the flag.
Rev. 5.00 Sep. 01, 2009 Page 320 of 656
REJ09B0071-0500
3
Bit
2
1
0
2. This bit is cleared by DTC only when DISEL = 0 with the transfer counter other than 0.
Bit Name
PER
TEND
MPB
MPBT
Initial
Value
0
1
0
0
R/W
R/(W) *
R
R
R/W
1
Description
Parity Error
Indicates that a parity error occurred during reception
using parity addition in asynchronous mode, causing
abnormal termination.
[Setting condition]
When a parity error is detected during reception
If a parity error occurs, the receive data is transferred to
RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the PER flag is
set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its previous state
when the RE bit in SCR is cleared to 0.
Transmit End
Indicates that transmission has been ended.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous state
is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
When 0 is written to TDRE after reading TDRE = 1
When the DTC *
request and transfer transmission data to TDR
(H8S/2268 Group only)
2
is activated by a TXI interrupt
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