DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 420
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 13 Serial Communication Interface (SCI)
Figure 13.31 shows a flowchart for transmission. In the H8S/2268 Group, a sequence of transmit
operations can be performed automatically by specifying the DTC to be activated with a TXI
interrupt source. In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND
flag in SSR is set, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If
the TXI request is designated beforehand as a DTC activation source, the DTC will be activated
by the TXI request, and transfer of the transmit data will be carried out. At this moment, when the
DISEL bit in DTC is 0 and the transfer counter is other than 0, the TDRE and TEND flags are
automatically cleared to 0 when data is transferred by the DTC. When the DISEL bit in the
corresponding DTC is 1, or both DISEL bit and the transfer counter are 0, flags are not cleared
although transfer data is written to TDR by DTC. Consequently give the CPU an instruction of
flag clear processing. In addition, in the event of an error, the SCI retransmits the same data
automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not
activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes
in the event of an error, including retransmission. However, the ERS flag is not cleared
automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an
ERI request will be generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC, it is essential to set and enable the DTC before carrying
out SCI setting. For details of the DTC setting procedures, refer to section 8, Data Transfer
Controller (DTC).
Rev. 5.00 Sep. 01, 2009 Page 368 of 656
REJ09B0071-0500
TDRE
TEND
FER/ERS
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated. Writing transmit data to TDR transfers the next transmit data.
Ds
Transfer to TSR from TDR
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 13.29 Retransfer Operation in SCI Transmit Mode
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer to TSR from TDR
Retransferred frame
(DE)
Ds D0 D1 D2 D3 D4
Transfer to TSR
Transfer
frame n+1
from TDR
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