D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 11
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section
1.2 Block Diagram
Figure 1.1 Block
Diagram
2.5.1 Processor States
5.4 Memory-Mapped
Cache
5.4.1 Address Array
List of Items Revised or Added for This Version
Page
6
53
113
Description
ASERAM deleted from figure
ASERAM deleted from legend
Description amended
In the power-on reset state, the internal states of the CPU and the
on-chip supporting module registers are initialized. In the manual
reset state, the internal states of the CPU and registers of on-chip
supporting modules other than the bus state controller (BSC) are
initialized.
the register configurations in the relevant sections for further
details.
Description amended
This operation is used to invalidate the address specification for a
cache. Write back will take place when the U bit of the entry that
received a hit is 1. Note that, when a 0 is written to the V bit, a 0
should always be written to the U bit of the same entry, too.
CPG/WDT
INTC
UDI
External bus
interface
BRIDGE
Rev. 5.0, 09/03, page ix of xliv
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