D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 400
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev. 5.00, 09/03, page 354 of 760
Figure 11.6 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
Note: In transfer between external memories, with DACK output in the read cycle, DACK
(2) In indirect address transfer mode, the address of memory in which data to be transferred is
CKIO
A25 to A0
CSn
D31 to D0
RD
WEn
DACKn
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
stored is specified in the transfer source address register (SAR3) in the DMAC.
Consequently, in this mode, the address value specified in the transfer source address
register in the DMAC is read first. This value is temporarily stored in the DMAC. Next,
the read value is output as an address, and the value stored in that address is stored in the
DMAC again. Then, the value read afterwards is written to the address specified in the
transfer destination address; this completes one DMA transfer. 16-byte transfer is not
possible.
Figure 11.7 shows an example. In this example, the transfer destination, the transfer
source, and the storage destination of the indirect address are 16-bit external memories,
and transfer data is 16 or 8 bits. Figure 11.8 shows an example of the transfer timing.
output timing is the same as that of CSn.
Data read cycle
Transfer source
(1st cycle)
address
Transfer destination
Data write cycle
(2nd cycle)
address
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