D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 531
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.5
Note the following points when using the SCI.
SCTDR Writing and TDRE Flag: The TDRE bit in the serial status register (SCSSR) is a status
flag indicating loading of transmit data from SCTDR into SCTSR. The SCI sets TDRE to 1 when
it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE
bit state. If new data is written in SCTDR when TDRE is 0, however, the old data stored in
SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing
transmit data to SCTDR, be sure to check that TDRE is set to 1.
Simultaneous Multiple Receive Errors: Table 14.14 indicates the state of SCSSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs, the SCRSR
contents cannot be transferred to SCRDR, so receive data is lost.
Table 14.14 SCSSR Status Flags and Transfer of Receive Data
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity error 1
X: Receive data is not transferred from SCRSR to SCRDR.
O: Receive data is transferred from SCRSR to SCRDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI
receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Sending a Break Signal: The TxD pin I/O condition and level can be determined by means of the
SCP0DT bit in the port SC data register (SCPDR) and bits SCP0MD0 and SCP0MD1 in the port
SC control register (SCPCR). This feature can be used to send breaks. To send a break during
serial transmission, clear the SCP0DT bit to 0 (designating low level), then clear the TE bit to 0
(halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of
the current transmission state, and 0 is output from the TxD pin.
Usage Notes
RDRF
1
0
0
1
1
0
SCSSR Status Flags
ORER
1
0
0
1
1
0
1
FER PER
0
1
0
1
0
1
1
Rev. 5.00, 09/03, page 485 of 760
0
0
1
0
1
1
1
Receive Data Transfer
SCRSR
X
O
O
X
X
O
X
SCRDR
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