D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 366
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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10.3.8
When a bus release request (BREQ) is asserted from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output The bus is not
released during burst transfers for cache fills or write-back, or TAS instruction execution between
the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that are
generated when the data bus width is shorter than the access size; i.e. in the bus cycles when
longword access is executed for the 8-bit memory. At the negation of BREQ, BACK is negated
and bus use is restarted See Appendix A.1, Pin States, for the pin states when the bus is released.
The SH7709S sometimes needs to retrieve a bus it has released. For example, when memory
generates a refresh request or an interrupt request internally, the SH7709S must perform the
appropriate processing. The SH7709S has a bus request signal (IRQOUT) for this purpose. When
it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus release
request receive the assertion of the IRQOUT signal and negate the BREQ signal to release the bus.
The SH7709S retrieves the bus and carries out the processing.
Rev. 5.00, 09/03, page 320 of 760
CKIO
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Bus Arbitration
Area m inter-access wait specification
Area m read
T
1
Figure 10.40 Waits between Access Cycles
T
2
Twait
Area n space read
T
1
Area n inter-access wait specification
T
2
Twait
Area n space write
T
1
T
2
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