D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 293
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bits 6 to 3—Address Multiplex (AMX3, AMX2, AMX1, AMX0): Specify address multiplexing
for synchronous DRAM.
For Synchronous DRAM Interface:
Notes: 1. Can only be set when using a 16-bit bus width.
Bit 2—Refresh Control (RFSH): The RFSH bit determines whether or not synchronous DRAM
refresh operations are is performed. If the refresh function is not used, the timer for generation of
periodic refresh requests can also be used as an interval timer.
Bit6:
AMX3
1
0
0
Except above value
Bit 2: RFSH
0
1
2. Can only be set when using a 32-bit bus width.
Bit5:
AMX2
1
1
0
Bit 4:
AMX1
0
1
0
1
0
Description
No refresh
Refresh
Bit 3:
AMX0
1
0
0
1
1
0
Description
The row address begins with A10 (The A10 value is output at
A1 when the row address is output. 4M
products)
The row address begins with A11 (The A11 value is output at
A1 when the row address is output. 8M
products) *
The row address begins with A9 (The A9 value is output at A1
when the row address is output. 1M
products)
The row address begins with A10 (The A10 value is output at
A1 when the row address is output. 2M
products, 2M
The row address begins with A9 (The A9 value is output at A1
when the row address is output. 512k
products) *
Begin synchronous DRAM access after setting AMX3 to 0 =
*1**
Reserved (Setting prohibited)
1
2
16-bit
4-bank products)
Rev. 5.00, 09/03, page 247 of 760
16-bit
32-bit
16-bit
16-bit
8-bit
4-bank
4-bank
4-bank
(Initial value)
(Initial value)
4-bank
4-bank
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