D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 206

• Manufacturer Part Number: D6417709SF167BV
• Description: IC SUPER H MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417709SF167BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.2.8
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the
break conditions of channel B. A power-on reset initializes BBRB to H'0000.
Bits 15 to 8—Reserved: These bits are always read as 0. These bits are always read as 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select B (CDB1, CDB0): Select the CPU cycle or
DMAC cycle as the bus cycle of the channel B break condition.
Bit 7: CDB1
0
*
1
*: Don’t care
Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1, IDB0): Select the instruction
fetch cycle or data access cycle as the bus cycle of the channel B break condition.
Bit 5: IDB1
0
1
Rev. 5.00, 09/03, page 160 of 760
Initial value:
Initial value:
Break Bus Cycle Register B (BBRB)
R/W:
R/W:
Bit:
Bit:
Bit 6: CDB0
0
1
0
Bit 4: IDB0
0
1
0
1
CDB1
R/W
15
—
R
0
7
0
CDB0
R/W
14
—
R
0
6
0
Description
Condition comparison is not performed
The break condition is the CPU cycle
The break condition is the DMAC cycle
Description
Condition comparison is not performed
The break condition is the instruction fetch cycle
The break condition is the data access cycle
The break condition is the instruction fetch cycle or data access
cycle
IDB1
R/W
13
—
R
0
5
0
IDB0
R/W
12
—
R
0
4
0
RWB1
R/W
11
—
R
0
3
0
RWB0
R/W
10
—
R
0
2
0
SZB1
R/W
—
R
9
0
1
0
(Initial value)
(Initial value)
SZB0
R/W
—
R
8
0
0
0