D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 461
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13.2.8
The year counter (RYRCNT) is an 8-bit readable/writable register used for setting/counting in the
BCD-coded year section of the RTC. The least significant 2 digits of the western calendar year are
displayed. The count operation is performed by a carry for each year of the month counter.
The range that can be set is 00–99 (decimal). Errant operation will result if any other value is set.
Carry out write processing after halting the count operation with the START bit in RCR2.
RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result
of 0. The year counter value: 00 is included in leap years.
13.2.9
The second alarm register (RSECAR) is an 8-bit readable/writable register, and an alarm register
corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the ENB
bit is set to 1, a comparison with the RSECCNT value is performed. From among the
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an RTC alarm interrupt is generated.
The range that can be set is 00–59 (decimal) + ENB bit. Errant operation will result if any other
value is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields
are not initialized and retain their contents by a manual reset, or in standby mode.
Initial value:
Initial value:
Year Counter (RYRCNT)
Second Alarm Register (RSECAR)
R/W:
R/W:
Bit:
Bit:
ENB
R/W
R/W
—
7
7
0
R/W
R/W
—
—
6
6
10 years
10 seconds
R/W
R/W
—
—
5
5
R/W
R/W
—
—
4
4
R/W
R/W
—
—
3
3
Rev. 5.00, 09/03, page 415 of 760
R/W
R/W
—
—
2
2
1 second
1 year
R/W
R/W
—
—
1
1
R/W
R/W
—
—
0
0
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