AT90PWM1-16MU Atmel, AT90PWM1-16MU Datasheet - Page 19

• Manufacturer Part Number: AT90PWM1-16MU
• Description: IC AVR PWM 8KB FLASH 16MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM1-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3
6.3.1
6.3.2
4378C–AVR–09/08
EEPROM Data Memory
EEPROM Read/Write Access
The EEPROM Address Registers – EEARH and EEARL
Figure 3. On-chip Data SRAM Access Cycles
The AT90PWM1 contains 512 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see
Downloading” on page
mands” on page 223
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to
run at a voltage lower than specified as minimum for the clock frequency used. For details on
how to avoid problems in these situations
24.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
Bit
15
–
Address
clk
Data
Data
WR
CPU
RD
respectively.
14
234, and
–
Compute Address
13
–
“Parallel Programming Parameters, Pin Mapping, and Com-
T1
Memory Access Instruction
12
–
seeSee “Preventing EEPROM Corruption” on page
11
–
Table
Address valid
T2
10
–
2. A self-timing function, however, lets
9
–
Next Instruction
EEAR8
AT90PWM1
8
T3
EEARH
“Serial
19
CC