AT90PWM1-16MU Atmel, AT90PWM1-16MU Datasheet - Page 80

• Manufacturer Part Number: AT90PWM1-16MU
• Description: IC AVR PWM 8KB FLASH 16MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM1-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.2
14.2
14.3
80
Timer/Counter Clock Sources
Counter Unit
AT90PWM1
Registers
The definitions in
Table 19. Definitions
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B).
event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Out-
put Compare interrupt request.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
14-2
Figure 14-2. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surroundings.
See “Using the Output Compare Unit” on page 106.
“Timer/Counter0 and Timer/Counter1 Prescalers” on page
DATA BUS
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is depen-
dent on the mode of operation.
TCNTn
Table 19
are also used extensively throughout the document.
direction
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
for details. The compare match
Clock Select
( From Prescaler )
Detector
Edge
76.
4378C–AVR–09/08
Tn
T0
).
Figure