ATTINY25-15MZ Atmel, ATTINY25-15MZ Datasheet - Page 93

• Manufacturer Part Number: ATTINY25-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-15MZ

• Package / Case: 20-QFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 6
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: UART, SPI, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 4
• Height: 0.75 mm
• Length: 4 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15. Dead Time Generator
7598H–AVR–07/09
The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving
external power control switches safely. The Dead Time Generator is a separate block that can
be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for
the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B). The sharing
of tasks is as follows: the timer/counter generates the PWM output and the Dead Time Genera-
tor generates the non-overlapping PWM output pair from the timer/counter PWM signal. Two
Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjust-
able and the PWM output and it’s complementary output are adjusted separately, and
independently for both PWM outputs.
Figure 15-1. Timer/Counter1 & Dead Time Generators
The dead time generation is based on the 4-bit down counters that count the dead time, as
shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can
divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of
dead times that can be generated. The prescaler is controlled by two control bits DTPS11..10
from the I/O register at address 0x23. The block has also a rising and falling edge detector that
is used to start the dead time counting period. Depending on the edge, one of the transitions on
the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The compara-
tor is used to compare the counter with zero and stop the dead time insertion when zero has
been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register,
depending on the edge of the PWM generator output when the dead time insertion is started.
Figure 15-2. Dead Time Generator
PWM1x
T/C1 CLOCK
DEAD TIME
PRESCALER
DTPS11..10
DT1AH
DT1AL
PCKE
T15M
PCK
CK
CLOCK CONTROL
DEAD TIME GENERATOR
OC1A
PWM1A
OC1A
TIMER/COUNTER1
PWM GENERATOR
4-BIT COUNTER
COMPARATOR
I/O REGISTER
DT1x
DEAD TIME GENERATOR
OC1B
PWM1B
OC1B
ATtiny25/45/85
DT1BH
DT1BL
OC1x
OC1x
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