ATMEGA324PA-AU Atmel, ATMEGA324PA-AU Datasheet - Page 23

MCU AVR 32K FLASH 20MHZ 40-TQFP

ATMEGA324PA-AU

Manufacturer Part Number
ATMEGA324PA-AU
Description
MCU AVR 32K FLASH 20MHZ 40-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA324PA-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATQT600
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Package
44TQFP
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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7.5
8272A–AVR–01/10
I/O Memory
The I/O space definition of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is
shown in
All ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P I/Os and peripherals are placed
in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD
instructions, transferring data between the 32 general purpose working registers and the I/O
space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the
SBI and CBI instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the
I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to
these addresses. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains three General Pur-
pose I/O Registers, see
storing any information, and they are particularly useful for storing global variables and Status
Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-
accessible using the SBI, CBI, SBIS, and SBIC instructions.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
”Register Summary” on page
”Register Description” on page
551.
24. These registers can be used for
23

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