ATMEGA329P-20MN Atmel, ATMEGA329P-20MN Datasheet - Page 155

• Manufacturer Part Number: ATMEGA329P-20MN
• Description: IC MCU AVR 32K 20MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.10 Register Description
17.10.1
8021G–AVR–03/11
TCCR2A – Timer/Counter Control Register A
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare
match is forced on the Waveform Generation unit. The OC2A output is changed according to its
COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the
value present in the COM2A1:0 bits that determines the effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 17-2.
Note:
• Bit 5:4 – COM2A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be
set in order to enable the output driver.
Bit
(0xB0)
Read/Write
Initial Value
Mode
0
1
2
3
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
146.
WGM21
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
Waveform Generation Mode Bit Description
FOC2A
W
7
0
WGM20
(PWM2)
WGM20
0
1
0
1
R/W
6
0
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
COM2A1
R/W
5
0
COM2A0
R/W
4
0
WGM21
R/W
3
0
ATmega329P/3290P
Table 17-2
(1)
TOP
0xFF
0xFF
OCR2A
0xFF
CS22
R/W
2
0
and
Update of
OCR2A at
Immediate
TOP
Immediate
BOTTOM
CS21
R/W
1
0
”Modes of Operation”
CS20
R/W
0
0
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
TCCR2A
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