ATMEGA329P-20MN Atmel, ATMEGA329P-20MN Datasheet - Page 62

• Manufacturer Part Number: ATMEGA329P-20MN
• Description: IC MCU AVR 32K 20MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.4
12.3.5
12.3.6
12.3.7
8021G–AVR–03/11
PCMSK3 – Pin Change Mask Register 3
PCMSK2 – Pin Change Mask Register 2
PCMSK1 – Pin Change Mask Register 1
PCMSK0 – Pin Change Mask Register 0
• Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30...24
Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT30:24 is set and the PCIE3 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT30:24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Note:
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit
(0x6D)
Read/Write
Initial Value
Bit
(0x73)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
Bit
(0x6B)
Read/Write
Initial Value
1. PCMSK3 and PCMSK2 are only present in ATmega3290P.
PCINT23
7
PCINT7
R/W
0
PCINT15
R/W
R/W
7
0
R
7
0
7
0
–
PCINT22
R/W
6
PCINT6
0
PCINT30
PCINT14
R/W
R/W
R/W
6
0
6
0
6
0
(1)
(1)
PCINT21
5
PCINT5
R/W
0
PCINT29
PCINT13
R/W
R/W
R/W
5
0
5
0
5
0
PCINT20
4
PCINT4
R/W
0
PCINT28
PCINT12
R/W
R/W
R/W
4
0
4
0
4
0
3
PCINT3
R/W
0
PCINT19
PCINT11
PCINT27
R/W
R/W
R/W
3
0
3
0
3
0
ATmega329P/3290P
2
PCINT2
R/W
0
PCINT18
PCINT26
PCINT10
R/W
R/W
R/W
2
0
2
0
2
0
1
PCINT1
R/W
0
PCINT17
PCINT25
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
0
PCINT0
R/W
0
PCINT16
PCINT24
PCINT8
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK0
PCMSK2
PCMSK3
PCMSK1
62